1. Field of the Invention
The present invention relates to an auto-precharge control signal generating circuit and method for a semiconductor memory device, and particularly to an auto-precharge control signal generating circuit and method for a synchronous semiconductor memory that regulates write recovery time.
2. Description of the Related Art
A precharge operation in dynamic random access memories (DRAMs) may be performed on an active bank or chip by asserting a precharge command. The precharge command may be asserted after an active command. A precharge operation may also be performed by an auto-precharge command. Typically, the auto-precharge command is asserted at the same time as a burst read command or burst write command. This is usually accomplished by asserting a logical high on an ADDRESS 10 pin or an AP pin. The auto-precharge with burst write operation is used to perform a precharge operation automatically after a given write recovery time (tWR) from the last data input, after writing the data in an amount indicated by the burst length provided with the read/write command.
The write recovery time tWR may be defined as the minimum number of clock cycles required to complete a write operation of the last data input and is calculated by dividing tWR by a clock cycle time and rounding up to the next highest integer.
FIG. 1 is a block diagram illustrating a precharge operation in a conventional synchronous dynamic random access memory (SDRAM). In FIG. 1, an SDRAM device 100 includes a memory cell array 110, a word line driver 120, and a precharge control circuit 130. The memory cell array 110 receives a word line signal WL and outputs data DATA. The word line driver 120 outputs the word line signal WL according to an active signal ACTIVE generated from an ACTIVE COMMAND or a PRECHARGE COMMAND. The precharge control circuit 130 receives the active signal ACTIVE, a write signal WRITE generated from a WRITE COMMAND, an auto precharge signal AUTO_PRC generated from an AUTO-PRECHARGE COMMAND and a clock signal CLOCK.
The active signal ACTIVE is generated according to an ACTIVE COMMAND or PRECHARGE COMMAND. The active signal ACTIVE is also generated by the precharge control circuit 130. The clock signal CLOCK is used as the reference for all SDRAM operations. All operations may be synchronized to the positive edge of the clock signal CLOCK.
FIG. 2 is a timing diagram that illustrates the operation of the conventional SDRAM of FIG. 1. At clock cycle C1, the ACTIVE COMMAND is supplied, whereby an internal operation activation designating active signal ACTIVE is rendered active as a memory cell array select operation commence designating signal. In response to the active signal ACTIVE, the word line driver circuit 120 acting as a row related circuit is set to activate a word line signal WL.
At clock cycle C3 , a write command WRITE is applied together with a first data input DATA1. FIG. 2 illustrates a case where a burst length is four BL4, which is programmed and determined in a mode register set command timing. The burst write operation is used to write data into the SDRAM on consecutive clock cycles in adjacent internal column addresses which is generated from an internal column address generator depending on the burst length and burst sequence. By asserting a write command with a valid external column address, a burst write operation is initiated. The data inputs are provided for the initial column address in the same clock cycle as the burst write command. The internal column address generator is deselected at the end of the burst length, even though the internal writing is not completed. In response to this write command, a write operation designating signal WRITE is activated and driven to a high-level of the active state. After the write command with a predetermined burst length, the write signal WRITE is driven to a low-level of the inactive state. In the case that the active signal ACTIVE is disabled, the word line signal WL is also disabled, and thus the write operation is not performed on the memory cell array 110.
At clock cycle C7, the precharge command PRECHARGE COMMAND is applied. The active signal ACTIVE is driven to the low-level of the inactive state and then the word line signal WL is driven to the low-level of the inactive state. The time from clock cycle C6 of the last data input DATA4 to clock cycle C7 of the precharge command PRECHARGE COMMAND is called the write recovery time (tWR). Data DATA1 to DATA3 is written to memory cell array block 110. However, it takes a fixed writing time to write the last data DATA4 before the word line signal WL is shut off. Usually this write time includes passing a data input buffer (not shown), passing a data line and bit line (not shown) which have resistance and/or capacitance load. It is assumed that it takes 10 nanoseconds (ns) at minimum to finish writing the last data DATA4.
FIG. 3A is a second timing diagram that illustrates the conventional precharge operation of the block diagram of FIG. 1. FIG. 3A illustrates the high-frequency operation case, where a clock cycle period (tCC) is less than 10 ns. The minimum write time 10 ns is more than the clock cycle period, so tWR should be determined to be two clock cycle periods.
FIG. 3B is a third timing diagram that illustrates the conventional precharge operation of the block diagram of FIG. 1. FIG. 3B illustrates the low-frequency operation case, where a clock cycle period (tCC) is more than 10 ns. The minimum write time 10 ns is less than the clock cycle period, so the tWR should be determined to be one clock cycle period. As illustrated in FIG. 3A, clock cycle C7 is redundant, which decreases the performance of the SDRAM.
FIG. 3C is a fourth timing diagram that illustrates the conventional auto-precharge operation of the block diagram of FIG. 1. At clock cycle C3 , a write command WRITE is applied together with an auto-precharge command AUTO-PRECHARGE COMMAND. The auto-precharge operation begins at clock cycle C8. FIG. 3C illustrates the high-frequency operation case, where a clock cycle period (tCC) is less than 10 ns. The minimum write time 10 ns is more than the clock cycle period so tWR should be determined to be two clock cycle periods.
FIG. 3D is a fifth timing diagram that illustrates the conventional auto-precharge operation of the block diagram of FIG. 1. FIG. 3D illustrates the low-frequency operation case, where a clock cycle period (tCC) is more than 10 ns. The minimum write time 10 ns is less than the clock cycle period, so tWR should be determined to be one clock cycle period. As illustrated in FIG. 3D, clock cycle C7 is redundant, which decreases the performance of the SDRAM.
SDRAMs employing other conventional auto-precharge operations are disclosed in U.S. Pat. Nos. 6,343,040, 6,215,711, 5,748,560, and Re36,532.